Digital system with error elimination



June 30, 1959 R. T. JAMES ET AL 2,892,388

DIGITAL SYSTEM WITH ERROR ELIMINATION Filed Feb. 10, 1958 8 Sheets-Sheet 1 ATTORNEY' June 30, 1959 R. T. JAMES ET AL 2,892,888

DIGITAL SYSTEM WITH ERROR ELIMINATION Filed Feb. l0, 1958 8 Sheets-Sheet 2 PA Rl TY CHECK Cl/PCU/ T (76- L ,NE srA/ar fra sla/VAL 7D/34; oA rA fao Y 'RECE/VER TIM/NG /82 lY 1 .sn-Rr STA/a7' D/G/zAL Low D/a/TAL 9454; DATA PAss I il-VE oArA DL mmv@ y TRA/vs. F/LZ'ER I 98 RIEC. T/M//ve kas 88 l k9o R. IJA MES NVENTORS A. E. RUPPEL ATTORNEY June 30, 1959 R. T. JAMES ET AL 2,892,888

DIGITAL SYSTEM WITH ERROR ELIMINATION Filed Feb. 10, 195e 8 Sheets-Sheet 3 VRYQ All.

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ATTORNEY June 30, 1959 R. T. JAMES ET AL 2,892,888

DIGITAL SYSTEM WITH ERROR ELIMINATION Filed Feb. 10, 1958 8 Sheets-Sheet 4 A 7' TORNEI June 30, 1959 Filed Feb. '10, 1958 PULSE /NPUT SGNALS FROM ERROR CHECK/NG DEV/CES MAX/MUM DELA Y R. T. JAMES ET'AL DIGITAL sYsTEM WITH ERROR ELIMINATION 8 Sheets-Sheet 5 I-f-ZO/ BIST FLOP CA T HODE CA THODE PAR/TY E l/ CATHODE CAT HODE R CAT HODE CAT HODE CAT HODE B/S TABLE FL /P- i207 FLOP CAI-Hoof co/vD. 7

RESET PULSE Mo/vosrAaLE FL /P-FLoP DELAY CATHODE PULSE SHAPER SART D/PULSE FROM DOR /N C /RCU/ 7' W/ T h' READOUT PULSE R. -r JAMES' MEMO/,"5 ,4. RU/PEL ATTORNEY June 30, 1959 R. T. JAMES ETAL 2,392,888

DIGITAL SYSTEM WITH ERROR ELIMINATION Filed Feb. 10. 1958 8 sheets-sheet e 1/Com 9 F/G.

OUTPUT 0F OUTPUT OF WORD STORAGE A WORD STORAGE B AL A RM S/GNAL 7'0 /ND/ CA TE /NTERRUPTED DA TA START R. Z JAMES /A/VENTORS A E RUP/,EL

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June 30, 1959 R. T. JAMES ET AL 2,892,888

DIGITAL sys-TRM WITH ERROR ELIMINATION 8 Sheets-Sheet 7 Filed Feb. 10, 1958 ATTORNEY June 30, 1959 R. T. JAMES ET AL 2,892,888

DIGITAL SYSTEM WITH ERROR ELIMINATION Filed Feb. 1o. 195e 8 Sheets-Sheet 8 ATTORNEY '.quently l'subject to transmission impairments.

vsignals. error check signalwwhich -is ythencombined *with conventional .digital :error-check signals; andthe transmitted digital .information is corrected in Yaccordance ywith the Acombined check signals.

{'DIGITAL`SYSTEM`-WITH ERROR ELIMINATION `fRichardfl.James, Gentral Valley; and Alfred' E.f-Ruppel,

."'East Rockaway, U'NJY.; said i James assignor uto American-Telephone and fTelegr-aph--Gompana corporation yof New York;` said rRuppel -assignor to Beil Telephone Laboratories;incorporated,New York, N.Y., a corpof ration of NeW'York Application'fFebruary 10, 1958,' Serial'No. 714,300

-13 Claims. (Cl. 178423) This invention relatesto digital data v.processing ap "paratus-and morespecifcally to-errordetection and cor` rection systems.

In the transmissionof digital informationfrom a source lto autilization circuit, thel connecting data link is fre- Many schemes have been proposed previously for detecting Lor 'i correcting 4errors which are-introduced Ainto'- the..1:rans emitted idigitalI information. .The simplest formof error detection could involve the transmission of each digit Errors couldwbe detectedby z'the -differencef-in parityl check =digit1= is a digit Which V-is-.r added.to a code :group to make ythe sum `of the :digits-'mathe vcodefgroup either :odd :or t even, 1, depending on the @type r of g parity ,check which 'is beingremployed. hus,: for fexample, :if =anod`d :parity check-Were performed.l `on?the^code.:gro1.tp 1101l01,:.the-:parity check fbit would f-be ia' 'ff1"fft'ovmake llthetotal numberof .1.s.:odd. vBy formingzparitychecks over'ldiiferent groups-of information digits, Isfuiicient addif tional icheck information :may :befprovided V:to permit correction of .lthefreceivedfmessage :'Assthe-.error corfrection capabilities :of: thecodes :are increased, .-hoWever, :the redundancy zof'the'ztransrnittedrmessage islcorrespondingly increased,Iand'l-therrate aoffrtransmission.ofsignals is therefor-reI substantially: reduced.

Accordingly,Y o'neoibject. ofiithe present'. inventionis to vimprove :error :detection and i correction` systems.

'In :accordance `lwith 4the :present invention, itnoise '1 hits on data-links Aarefdetected :and converted 4`into 'rdigital The 4resultant noisev indicationylconstitutes :fan

Forexample, if the sameinformationV istransmittedvalong two separate transmission facilities,-thereceived-messages may l'be-compared on a `bitlbybit basis and the noise hits on each'facility may be detected. .If 'thelbit-by-bit comparison circuit indicatesan error .an'd '.the` noise detectionlcircuit shows' 'that fone 'of the facilitiesiwaslit' by aiburst'of noise,'switch ing'circuits may Ibe operated to SeleCV'theWunaifected facility. 'Accordingly,-` the' "message 'is' `transmitted "in "its correct formover` the'un'alfected`V facility to the utilization circuitAVA associated -=With the `receiver.

`-'In accordance'wi'th "an important ffeature-'of- 'thetin- 70ftio`n circuit 22. *vention, "a `source of ldigital IinformationfsignalsJanii a vutilization 1 circuit-are intercoupled 'by a 1digital.1encoder,

United States Patent SOL . at leastone-data link, and ardecoder. .decoder include circuitry `for transmitting the digital in- Patented June 30, 1959 The encoder and Aformation'signals with increased redundancy .to permit error-detection, noiseihits on the data link are detected .and--quantized toprovide additional errordetectionsig- Iralsfanderrors in the received information signals-are eliminated through the use o-f both types of digital-error detection information.

In accordance with another feature of Ithe-invention, digitalsignals,-` are.- transmittedV over two separate l'facilities fand `arelcompared on-a bit-by-bit basis, circuits vvfor devtectingrnoiseon eachof ythe -tWo facilities are,.provided, fand switching circuitsare-energized inftheevent offerror #indications by -the bit-by-bit comparator to fselect the i channel which is unaffected byenoise' hits.

r-Iny accordance YWith-a further feature of the. invention,

Vvtransmitted .digital'signals are provided with :additional iparrty. check Ksignals lfor rerror detection, and anfaddiuonal n circuitris. vprovided for detecting @and :quantizing 20 noisesignals. Inthe event ofvafparity check failure,rthe

fdigit'alnoise signals are employed to identify the erroneous t digital signals `and :permit their` elimination.

accordance `with .an additional featuref of the :in-

A"ven'tionycheckfoutput signals from the"bitbybit comnparison circuitry, the. paritychecking circuitry, and "the noise'd'et'ection arrangements fdescribedin Vthe foregoing xtwo ..paragraphs'rnayz be combined to produce a system diavlngpowerful' error correction characteristics.

.@ne advantagelofthe presentxerror correction circuitry fas icontrasted'- lwith vthe conventional error correctonf'circuits which .merelyfremployLa large amount of redundant -rinformationz'is thereduction -in the 'amount of digital :fsignalsfwhich'fmust be transmitted. .This is possiblefas :.aflfresult. ofl'the 'digital rcheck informationderived from the-.incise hits. `A larger proportion of signal informa- V*tion 'may`therefore betransmitted over transmissionV facili- V4itles for any given level'of. error correction for theover- --allilsystem.

A complete understanding of this invention Vands'of thesefand various otherfeatures-Lthereof may be gained *from consideration lofft'he following detailed --description fan'di thev accompanying drawing, :ini-which:

Fig. 1 is a blockldiagram ofladigital-datafhandling system withA provisionl Yfor error: elimination-v in 'accordance ffwi'thfthe? present invention;

Fig. :Zis 1a `block diagram of :a parityicheckzcircnit i associated withia digital data receiver;

vFig 3 is la' block circuit diagram of 'a noise 'detection circuit which may be associatediwith 'the interconnecting 'data I link of the system of `Fig. -1;

""Figs.-4land'5 together constitute a logic vcircuitdiagrarn -inaccor'dance with the invention vwhich 4may beutilized Ein'the.: circuit ofFig. l;

Fi'gs.- 6, Y"7,-8, and`9 arevcircuitldiagrams-of component circuitstwhich are employed in themore complex circuit 'fdiagramsof the present application;

*Figs lO'and 1l together constitute-anialternative-logic `circuit"diagram `in accordancewith the invention-which LAmay be included fin the circuit of Fig. l;

Fig. 12.shoWs-a frequency divisionmultiplexing error correction arrangement'in-'accordance with the present Linvention;v and L'Figs. *13 and l4'are time divisionfmultiplexingierror 'correction 'circuits irl-accordance with the present invention.

Referring more specifically to the drawing, Fig. lis a f block 'circuit diagram 'of an illustrative embodiment of the invention. `In Fig.` l, it is desired-to transmitidigitalisignalsV from' thesignal origination circuitry 20` to .theautiliza- The transmitted signalsare to :be-.fin ldigital'fform, rand will include successive ulgroups, or Y\Words,`=each including a standard nurnlbenofy binary `which is a single cycle of a sine wave.

digits, or bits. As developed in the signal origination circuitry 20, the start signal is in the form of a dipulse, Timing signals are provided by a standard sine wave signal source. Binary signals from the origination circuitry 20 are in the form of the presence or absence of dipulse signals in successive digit periods, as defined by successive cycles of the timing signal. In addition, a parity check signal is included in each Word of digital information provided by circuit 20.

The start, data, and timing signals are coupled to the bridge circuit 24 on leads 26, 2S, and 30, respectively. From the bridge circuit 24, the three signals are coupled to both of the digital data transmitters 32 and 34. At the output of each of the digital data transmitters 32 and 34, the signals have the form indicated at 36. The wave form 36 is an amplitude modulated signal which includes start pulse indications and additional signals. The start pulses designated 38 mark the beginning of successive words and have an amplitude which is greater than the digital signals included in each word. The space between successive start pulses is divided into time slots, or digit periods, as indicated by the equally spaced vertical dashdot lines in the wave form 36. The digital signals are represented yby the magnitude of the alternating current carrier signal in successive time slots. Thus, a binary l is represented by a signal having a relatively large magnitude, whereas a binary is represented by a low amplitude signal in a given time slot. The frequency of the carrier signal of the wave form 36 may, for example, be approximately 2,000 cycles. The digital data transmitters 32 and 34 include the conventional modulation circuitry required for transforming the signals on leads 26, 28, and 30 into the form shown at 36.

In the system shown in Fig. 1, it is important that one error-free channel be available for signal transmission from the signal origination circuitry 20 to the utilization circuit 22. Accordingly, two alternative channels 40 and 42 are provided. These channels are preferably provided over geographically separated facilities, so that the likelihood of both channels being out at the same time is reduced.

At the receiving terminal or apparatus 43 shown at the right-hand side of Fig. 1, the signals derived from one of channels 40 or 42 are decoded and applied to the utilization circuit 22. The receiving terminal 43 includes the digital data receiver 44 and the noise circuit 46 coupled to channel 40. In the digital data receiver 44, start, data, and timing signals, such as those shown associated with leads 26, 28, and 30, are recovered. Similar digital data receiver and noise circuits 48 and 50 are associated with channel 42 at the receiving terminal.

It may be noted that channel 40 is also designated line A, and that channel 42 is also designated line B. Similarly, the various circuits in the receiving terminal associated with lines A and B are identified by the appropriate letter. In addition to signals registered by the noise detection circuits 46 and 50, other check information is obtained by the parity check circuits 52 and 54 associated 'with channels A and B, respectively. The correctness of the digital signals received on lines A and B is also checked by the bit-'by-bit comparison circuit 56. The three types of checking information are applied to the logic circuit 58. In the logic circuit 58, the various check signals are combined systematically to indicate the probability that the signal on either line A or line B is correct. Output signals from the logic circuit 58 are thereafter applied to the circuit selection and interruption switching circuitry 60.

One word of received data from lines A and B is stored in each of the word storage circuits 62 and 64. These storage circuits may, for example, be suitable shift register circuits having one stage for each bit of the received signal. Following the selection of channel A or B as bearing the correct signal information during a given Word period, the signals stored in either word storage circuit 62 or word storage circuit 64 are transmitted through to the utilization circuit 22. It must be mentioned, however, that if the logic circuit 58 indicates that the received information on both channels is probably erroneous, an interruption switch included in the circuit 60 is energized, and no information is transmitted to the utilization circuit 22. Under these circumstances, a signal is also applied to the alarm circuit 66 to indicate that some data has4 been deleted. The alarm circuit 66 may, for example, include a counter circuit to register the number of deleted words over a given period of time.

Normally, there will be a difference in the delay of the channels 40 and 42 which produces a staggered time of arrival of signals at the digital ydata receivers 44 and 48. This time differential is accommodated in various ways, as will be described in detail below. For example, the delay circuit 68 is required between the noise detection circuit 46 and the logic circuit 58 to insure simultaneous arrival of the signal from noise circuit 46 with check information from other sources. Similarly, the delay circuit 69 is required to equalize the delay from the two -data leads to the respective inputs of the bit-by-bit comparator 56.

Fig. 2 is a circuit diagram which shows the coupling of the parity check circuit to the output signals from the digital data receivers. In Fig. 2, the parity check circuit 70 includes the bistable flip-op 72 and the gate 74. The signals from the digital data receiver 76 include the start signal on lead 78, the data and parity check bit signals on lead 80, and the timing signal on lead 82. The bistable ip-op 72 is provided with steering circuits to form a single stage of a counter circuit. Thus, successive data signals on lead 80 set the ip-op 72 to opposite states. Although either even or odd parity signals could be used, in the present circuits an even parity check is employed. That is, an even parity check pulse is provided at the end of each word to make the total number of bits included in each word even. A parity error pulse is produced on lead 84 at the output of gate 74 if the bistable ip-op 72 indicates an odd number of bits included in a single word. The start pulse of the next successive word applies a signal to the gate circuit 74, and resets the bistable ip-op 72 to its initial state. If it is already in the initial state, no output signal is transmitted on lead 84. However, if it must be reset to the initial state, the transition pulse is applied through gate 74, which has been opened by the start signal, to the output lead 84.

Fig. 3 illustrates the arrangements for the noise detection circuitry. Shown in Fig. 3 are the digital data transmitter 86, the low pass ilter 88 associated with the transmitter, and various circuits associated with the receiver terminal including the digital data receiver 90, the high pass lter 92, the noise detector 94, and the level actuated alarm circuit 96. The noise detector 94 1s arranged to detect impulses outside the signaling band of the circuit. In the illustrative arrangement shown in Fig. 3, the noise detector is arranged to pick up signals above the normal data signal transmission band. Accordingly, the cut-ofi frequency of the low pass lter 88 is slightly above the signaling band, and the cut-off frequency of the high pass lter 92 is identical with that of the low pass lilter 88. Noise in the signaling band therefore does not reach the noise detector 94. When a noise burst including substantial high frequency components hits the line 98 interconnecting the low pass lter 88 and the digital data receiver 90, the noise pulse is transmitted through the high pass filter 92 to the noise detector 94. If the detected noise is above a predetermined threshold level, the noise alarm or noise signaling circuit 96 is energized, and a noise check pulse is produced on output lead 100. For the purposes of the block diagram circuit of Fig. 1, the noise detection circuits 46 and include allof the circuitsshownwithin-the dash- `As discussed above, the -circuitof Fig. l'provides Vvarious signals which may be utilized 'ffor checking receiveid 'data j comparison of thetwo 'receiveddata signals are available, jipari'tychecks foreach of the two received signals appear "at'the output of circuits 52 and 54, and "digital check fsignals indicating noise hits on the two'lines are also developed The logicv circuit '58 correlates'the three types vof error checking information mentioned above, and controls'the switching circuit60"shown in Fig. 1 to connect Yone ofthe two transmission 'channels' to 'the utilization circuit 22, Aor to interrupt 'signal'transmis'sion entirely.

Specifically, 'the results of aJbit-by-bit 5 `order to operate properly. It is therefore. desirable. to delete words 'when 'there considerable llikelihood` that the received'wordsare erroneous. p v Condition 5 is similar to conditionZ inlthat parity has "failed forone of the lines but.not"`for"t;he other, andthe .lineindicated as having a correct received code group by `the.parity"check also has notl been hit-by'fnoise. vIn the 'case of condition '5, line 'A1 appearstobear thec'orrect message. Accordingly, thisfline is selected.

"fCondition'6' corresponds to condition *3. `f In'condition `6`a`s in condition 3, "the'circuitlraving a valid parity Icheck has alsobeenhit'b'y noise. -In"thef caseo`f condition 6, this line is line yA. `r`Because'oftheconfiicting check signals, no `word-signal isl transmittedfto thev utiliza- The mode of operation ofthe logic circuit 58 may be 15 `tioncireuit' 22.

-. 'as indicated in 'the' following table.

Conditions 7` and-'8 lshowan error in theJ bitbybit coml"In'the foregoing table, E indicatesian error,` OKindifcates' no Ierror,'the letters A'y and B denote circuits `A "and B, the letter I indicates circuit interruption, `and NS denotes no selection. The no -`selection condition lactually means no change in selection, andthe switch remains in the previous channel selection position.

` In "Table I, ten input signal conditions'from the tive check circuits `are tabulated. These various possible input signal conditions will now be considered in order. First, *if* the bit-by-bit comparisongivesa-binary'signal (designated OK in Table I), indicating that the received 'words'i from channels 'A and yB are identical, logic'cir- `cuit 58VK does not change the selectionstate of the switch- -ing circuit 60. Thus, for example, 4if channel-A has been 4connected to the utilization circuit, itx-Will Aremainl con- 'nected to the utilization circuit.

Condition 2`in` Table I represents a Hcombination of check signals in which the bit-by-bit comparatorindicates an error, and ther parity check of the Word received on channel Ashows an'error and theparity check for "channel B indicates a correctly received word. The noise Acircuit associated with channel `A couldeither show a -eheck or no check, and thenoise circuit associated with ChanneLB shows noreceived'noise hits. VIny view of `the fact that both ftheparity check andthenoise detec- -tion circuit indicate no trouble on'channel B, signals e from th'is'channel are'l connected to the utilization cir- 'cuit 22.

Conditions -3 and 4^are 'such that it is considered inadvisable to select either channel. In bothI conditions 3 "andcondition 4, the bit-bybit comparator circuit indi- CatesA an error, andthe parity check for channel A' also indicates an error. In condition 3 of Table I, the parity -checkfor channel B indicates a valid received'code v4group but the noise circuit 'associated with channel B shows that this channel 'hasbeen hit` by noise. Under these circumstances, it is considered that neither'signal is likely to becorrect, and signal transmission is interrupted. `-Incondition 4, where both parity checks fail, interrup'tion is again considered desirable. As lshown in Fig. 1, `"the alarm circuit 66v may be energized when signal *transmission is'interrupted In passing, lit may be noted W.that theutilization circuit 22 requires a moderatelyv high degree of continuity in correctly received information in4 parison `while thepparity r :checks for bothsehannels are In; additions condition 71shows that .the -noise circuits 'have not been ienergized,` whereas..'condition 8 -indicates ythat'both` noise *circuits have been energized.

-Under these circumstances, `there-is'insuiiicient data to indicate which channels shouldfbe selectedpso the .circuit Vis interrupted for vone word period.

The conditions indicated'at 9 and 10 -aresimilar to those Vshown at 7 and 8 in'Table I in that the bit-by-bit comparator indicates=an\-'error,fandbothparity checks .are

satisfied. Howeverfone ofthenoise circuitshasbeen energized,whereas the other noise circuit hasnot been energized. Underthese: circumstances, the channelzwhich has not been aiected by noiseis selected.

`The=1ogic operations indicated by 'TableI :are implemented by thecircuitofFigs. 4wand15. The Ainputs to the-circuit of Figs..4 fand-52are the live error-checking signals and the start pulse signal from the digitalfdata receiver. .The `errori checking signals-are applied to the ve upper leads show-nto lthe leftffof-Figs.V 4 and 5. Speh-ciiic'allywtlieoutputffrom the fbit-by-bit comparator is applied1 on leadV N4 `to control the' state of the Ibistable 4flip-121011105. The parity lcheck-signals for lines A- and -B are applied onleads .106 and,.108 to control theV states of-ip-flops-ll and 11,2, respectively. The signals from the noise detection circuitsassociated withvlines-A.. and B are appliedon leads 114 and'116 Vto controlthe states of V.flip-flops 118 rand 120, respectively. Start signals from'the digital data receiverassociated with the .line having the maximumdelay are applied on`1ead'122 to the pulse Shaper circuit 124. Output'signals fromV the circuit1'24 are applied to both'the monostable'flip-iiop delaycircuit 126 yandthe cathodef'ollower 128. 4The 7 sign, and those which are less positive are marked with a minus sign, for the conditions mentioned above.

In the circuit of Figs. 4 and 5, an And gate is provided for each of the conditions 1 through 10. These And circuits each include two or more diodes, and are designated by the reference numerals 141 through 150 in the circuit of Figs. 4 and 5. Each group of diodes includes one diode which is coupled to the cathode follower 128 at the output of the pulse shaper circuit 124. The cathode follower supplies a read-out pulse to lead 152, which is connected to the lowermost diode in each of the And gates 141 through 150.

The mode of operation of the And gates 141 through 150 is conventional. More specifically, the voltage at the output of each And gate will be the voltage of the highest positive cathode follower. Therefore, if all of the cathode followers connected to a gate are in the negative, or less positive condition, the voltage at the to the And circuit 145 is `connected to the cathode foloutput of the And gate will be this negative voltage. f

The operation of the logic circuit of Figs. and under certain representative conditions set forth 1n Table I will now be considered. Considering condition 1, the

Ac- Y The resultant output pulse from And i to the upper input lead 156 of the bistable Hip-flop 158.

The circuit 158 controls the operation of the circuit interruption relay 160. When the bistable flip flop 158 is energized by a pulse on lead 156, the output of the cathode follower 162 is negative, and the output of the cathode follower 166 is positive. With a negative signal on lead 164 at the output of cathode follower 162 and a positive signal on lead 168 at the output of cathode follower 166, the diode 170 is forward-biased, and current is supplied to the coil 160 of the circuit interruption relay. When the lower lead 157 at the input of the Hip-flop 158 is energized, the polarity on leads 164 and 168 is reversed, the diode 170 is back-biased, and the circuit interruption relay 160 is not operated.

As mentioned above, the output signal from the And circuit 141, corresponding to condition 1 of Table I, energizes the upper input lead 156 of ilip-op 158. Under these conditions, the circuit interruption relay 160 is energized, thereby closing the data contacts of the relay.

It may also be noted that the lead 172 at the output 'L of cathode follower 131 is connected as an input to all of the remaining And gates 142 through 150 corresponding to conditions 2 through 10 of Table I. With this lead in the positive state, none of the And circuits 142 through 150 is energized. Accordingly, the state of the bistable flip-flop 174 Vcannot be changed. In view of the fact that the bistable ip-iiop 174 controls the selection of signals from channel A or channel B, no change in this selection is effected. Accordingly, the indicated lack of selection under condition 1 of Table I is verified.

As another illustrative example, the implementation of condition 5 of Table I will now be considered by reference to Figs. 4 and 5. Referring to Table I, it may be noted that condition 5 requires (1) that the bit-bybit comparator indicate an error, (2) that the parity check for channel A indicate a correct parity check, (3) that the parity check circuit for channel B indicate an error, and (4) that the noise circuit associated with channel A indicate that no noise hits occur during the word period in question. For the purposes of condition 5, the state of the noise detection circuit associated with channel B is immaterial. With the parity and the noise circuit both indicating that the signals received on channel A are correct, the preferred circuit selection indicated output signal.

lower 134 at the output of the A parity check flip-flop v110. With no signal being applied to lead 106, the flipliop remains in the state in which the output from cathode follower 134 is negative. The second of the ve required negative input signals to And gate 145 is there- ,i fore provided. The cathode follower 135 is coupled to the third input 180 of the And circuit 145. An error signal is applied to lead 108 to set bistable flip-hop 112 to the state in which the output from the cathode follower 135 is negative. The 4fourth input lead 182 to And circuit is connected to the cathode follower 138 at the output of the noise detector flip-flop 118 associated with channel A. With no signal received on lead 114, the output signal from cathode follower 138 is negative. The fifth and final input signal to And circuit 145 is provided by the read-out pulse applied to lead 152. The output signal from the And circuit 145 is applied to the upper input lead 184 of the bistable ilip-lop 174. The bistable hip-flop 174 controls the channel selection circuits. When a pulse is applied to lead 184 at the input to the bistable flip-flop 174, the cathode follower 186 has a negative output and the cathode follower 188 produces a positive Diode 190 and relay coil 192 are connected in series between the outputs of the two cathode followers 136 and 188. When input lead 184 is energized, the flip-Hop 174 is set to the state in which diode 190 is conducting and relay 192 is energized. Under these circtunstances, channel A is selected. When the ip flop 174 is operated to its other state, however, the diode 190 is back-biased, relaycoil 192 is not energized, and channel B is selected.

In the preceding paragraphs, the input leads to the And circuit 145 have been traced. ln addition, it has been shown that when the error check circumstances shown at condition 5 in Table I obtain, an output pulse from And circuit 145 is produced. This output signal enables the channel selection Hip-flop 174 to select channel A. It is clear, therefore, that the circuit of Fig. 5 is operative to fulfill the selection result indicated by condition 5 of Table I.

In the preceding description, it has been shown that the And circuits 141 and 145 control the interruption relay and the circuit selection relay 192 to perform the functions indicated under conditions 1 and 5 as set forth in Table I. In a similar manner, the And circuits 142 through 143 and 146 through 156 are operative to control the circuit selection and circuit interruption switching operations indicated by the corresponding entries in Table I. The exact details of the operation of each of the remaining And gates will therefore not be considered. From an over-all standpoint, however, it is evident that the logic circuit shown in Figs. 4 and 5 operates properly to apply successive words of digital information from channel A or channel B to the utilization circuit in accordance with Table I.

The circuits of Figs. 6 through 9 represent simplied building blocks or components which may be employed in the logic circuit of Figs. 4 and 5. Fig. 6 is a circuit which may be used as the pulse Shaper 124 of Fig. 5. The circuit transforms the dipulse input into a sharp negative-going pulse which is employed as the read-out pulse for the And circuits of Figs. 4 and 5. In Fig. 6, the diode 194 clips the positive half cycle of the input dipulse.. The triode 196 produces a positive output pulse, and this positive output pulse is inverted and squared up by the triode 198. An output differentiation circuit produces the desired negative-going output signal.

9 F.gz7 :Shows .-.e .simple .eenventiepel mepbetable .dip- -lopwliich also'includefssome delay. IThe. c1 tj, si re 1 charactefities ,tre provided .by tbe yttl.tempting current .eireuit which eebples .tbe rgrid Q-f ,epe 4tube te the plate ,et Ythe ether., and .thediteet .eurrept .eeupling of .the .grid .ef .the

tage@ iid v1.ditieps.ebtuipel.A is Seleet'ed .in preference@ ebeppe- .Cenditien .1.:2-ieeimi1ertee0nditiei1 1l with .the .exeeption.that.the.peritvebeek ter .eharmel :B tetherthen .ebenpeiA ieeerreet- .Channel .B .iS therefeteseleeted- In conditions 13 and 1 4, selection is rnadeon thejbasis `,second tube .to k the plate of the first. A dierentiating t5 of check signals at the output ofboth the parityand noise l irqpiit ,is t,again provided to produce `the .negative-going circuits for either channel A or B. In the case o f con- .output pulse. dition 13, Channel B is selected in View of the OK sig- Y iy .8 .Shewseeopventional.bistableip-ep-er multi- Vnels .from .the bit-.by-bit eemperater, ,and the ehennell r o r ,em-playing .triodea The l,grid-to-plate cross 10 parity and noise circuits. Similarly, referring .to conuphngs .are .,directcurrent couplings, yso that the cirdition 14, the check signals from the Channel A Parity cuit is stable `with either tube conducting. and noise circuits leadto the selection of channel A.

Ei-g. 9,is a conventional c athodefollower circuit. In- In .the Case of condition Al5, the bit-by-bit compara- .puteigpels ereepplied .tothe aridefthe triedeendepttor .and the two parity `cheek eireuits indieete '110.e1r0r, are produced across the cathode resistor. l5 While the noise circuits indicate the occurrence of noise Aslmeptepedebove, Table lend tbeeirepiteffigs- 4 hits during the time `period in Wheh .the Signale were and 5 indicatepnernodeofoperation and circuit implereceived. Under these circumstances, it is probable that jutentatien -ef :the legte .Circuit 5.58 :and `Switetiine ieireuit .beth received .code greups are eerreet, .end it .iS imped- 6 0 of lI-"igs, 4 and 5. For the purposes of Table I and sibleto givepreference toeither signal. Accordingly, no 4Figs. ,4 Yand 5,-the .presence of a bit-by-.bit check of the 20 change of selection is made. .signale trbmehenneleeend Weeeeneidered sueient The eireuit 0f Figs- 10 and .11 may be employed-t0 .to ,warrant noselection in the switching circuitry .6.0 implement Table II. 4In the circuit o f Figs. .1 0 and '11, pil-lig. 1. I nany circuit components are identical with those shown .A indre sophistieeted mede .ef Operation ef the .legie .in Figs- `4 and 5 and therefere are identified-.by the Seme circuit Vv`58 is set forth in Table II. The circuit for the 25 reference numerals. Because the logic circuitry is s orneirnplementation of Table II is designated Figs. l0 and 1l, what different, however, the And circuits corresponding it appears on two sheets o-f the drawing. T able II. is to conditions 1 through 15 of Table II have been given A set Zforth l 3 e l oyv. new `reference numerals 20,1.through 215. It may be Table ll t; Bit-by-lBit Parity Parity Noise Noise SwitchrGondition -Coniaraf Check-A Check-B Y Circuit A lCircuitB iln The .meaning .of .the symbols employed in Table II .has beenset f tiiebeve .id eenneetiep .with Table .1.- The =ee,tttiitiepe .1 tbreugb ,1.5 .O f liable .Il :may .best be considered by comparison with the conditions .of Table I. In the conditions deiined in Table I, it may be `recalled that no change in selection was required when the bit-hy-bit comparatorindicated no error. This was condition 1 of Table I. ,In Table II, some selectionaction takes place `with certain noise and parity check rconditions, even when ithe bit-by-'bit comparator indicates a check. f lhus, the first condition in TablesII indicates `no change in selection only when all live of the check circuits' have OK output signals.

Conditionsthrough 10.0f- .T able-I Icorrespond closely VS.to conditions 2 through 1 0 of Table gI. The only ditereppearpnder .eenditiens 3, 4, ende ef .Table r1.1- ;Lide the columnindicating the o utputof thebit-by-bit eempefetet tbe .indieetiep OK er E yeppeers in .Table -.feiewipe\eepidtiene 3, 4. .and 6, v.Nbereae ebb' .the designation ii-,3 appeared at these :points yin Table 1I. ema phyeieeletepdpbint,,eonditiete y3. 4., and 6 represu tsitations in which lthere .is suicient `contradiction Y jp,theresults indicated by j the parity check vand noise cir- ...wpits to-warrant interruption whether ornotthebt-byfbit I.etnpptweeter indieates aeheek- In Q nditign L111, the bit-by-bit comparator indicates a isbeelt., :the parity eiretlit .ter line .A .Shows a ,eheelc tbe parityteirepitfer lipeziedieetes enterrer, end .beth

.rei therapie., reirepits .ipdieete .e .eheek- Under these..eepf

.noted that V.the And circuit 201 correspondingto vcondi- .tion l of-Table ;I I has )several more inputsthanthecorrelspending And circuit 141 of Figs. 4 and 5. This .is a .resultcithe .requirement .thatall five check .signals indi- :eeted QKfinerderte produce the .desired .leek et .eelee- ,diodesof each A of the And gates 201 through 2115. The

relay circuits are .operated by connections lfrom the And .gates to .implement the switching operations shown in Teb-l@.11111 exactly the ,Samemannerthet the Cefleepbnt- .ine eiteuits of .F.iee y4 `air-1d 5 Werepperated ,teimbleipept Tabic .I. Accordingly, n o further detailed description o f Figs. ,l0 and ll is required.

Fig 1'2 shows a Vfrequency division multiplexing arrangement to which the principles ofthe invention are applicable. In fig. l2, start, data, and timing pulses are `routed tothe digital data transmitters 218 and 2120 yby the vvbridge circuit 2212. Signals `from the digital data transmitter`218 are passed through the .low pass `filter -224 and the mixing circuit -226 to the transmissionline 4228. AThe 1o..W.pass lter 224 eliminates high `frequency comPQnentS which might be lpresent in yharrnorlic f orin .in the signal from the'transrnittcr 218. vSignals from the .-dieitf'ddate transmitter 220 are paSSed-threpsb tbe delay .eiteut 2.3.0 t0 themedulater ..232- The medulater .2.512.

,combines modulated signals from the delay circuit 'with signals developed by the carrier oscillator 234. The

modulated signals originated by the data transmitter 220 are thus shifted in frequency at the output of the modulator 232. The band-pass filter 236 interconnecting the modulator 232 and the mixing circuit 226 blocks the transmission of signals outside the desired new signal frequency band. In the mixing circuit 226, the two sets of modulated signals are combined and applied to the transmission line 228 in different frequency bands.

At the receiving terminal, the modulated signals are coupled by the bridge circuit 238 to the low pass filter 240 and the band-pass ilter 242. The carrier oscillator 244 and the demodulator 246 shift the signals on channel B down to the normal signal modulation range. The resultant signals from the demodulator 246 are passed ,through the low pass filter 248. The signals at the output of the filter circuits 240 and 248 are applied to the data receivers and error reduction circuits designated 250. This circuitry corresponds to the entire receiver terminal circuitry shown at the right-hand side of Fig. 1.

The delay circuit 230 in the transmitting terminal of Fig. 12 introduces a delay which is greater than one digit period into the signals transmitted on channel B. Compensation for this delay is introduced in the circuit 250 at the receiver terminal. With the resulting dierence in delay, any errors caused by noise hits or switching, for example, occur durin-g different digit periods in the data words transmitted over the two channels, and hence will be detected by the checking circuits. The noise detection circuits included in circuit 250 may be coupled to a point before the filters 240 and 242, andv their output signals are delayed properly for association with the proper input signals. e

Two circuit arrangements for applying the principlesof time division multiplexing to the present data transmission system are shown in Figs. 13 and 14. Each of the circuit arrangements requires that the data bit rate on the transmission line be twice the data bit rate normally employed between the digital data transmitters and receivers.

In the transmitting terminal of the time division multi-V plexing arrangement of Fig. 13, the input data signal pulses are fed to a pulse width dividing circuit 252 where each of the mar signals is regenerated with a time period or width of one half of that of the normal input mark signals. The output of the pulse width divider 2,52 is coupled by the bridge circuit 254 to the mixing circuit 256 and the delay circuit 258. The delay circuit 258 has a delay of one digit period plus an even number of digit periods, where a digit period is measured at the output of the pulse divider 252. The one-digit period of delay is for the purposes discussed above in connection with the circuit of Fig. 12, the additional even number of bits being provided for interleaving the signals on channel B with those on channel A. The resulting interleaved signals are applied from the mixing circuit 256 to the digital data transmitter 260. Modulated output signals from the digital data transmitter 260 are transmitted along the line 262 to the bridge circuit 264. Channel A at the receiving terminal includes the delay circuit 266 having a delay equal `to that of the circuit 258 at the transmitting terminal. The receiving terminal also includes the digital data receivers 268 and 270, and theirassociated noise detection circuits 272 and 274. Timing signals for the digital data receivers 268 and 270 and for the noise circuits 27 2 and 27 4 are provided by the timing control circuit 276. The timing circuit 276 enables the noise circuits 272 and 274 during alternate time intervals so that they are only enabled during the time of reception of signals associated with channels A and B, respectively. Similarly, the digital data receivers 268 and 270 are enabled to detect alternate received bits from the transmis- 12 that shown in the receiving terminal of Fig. 13 is the same as that shown in Fig. 1, for example.

The system of Fig. 14 is very similar to that of Fig. 13. The principal difference lies in the transmission of successive words which are associated with channels A and B, rather than the transmission of interleaved bits associated respectively with the two channels. In Fig. 14 the start, data, and timing signals are applied to the storage circuit 278. The start signals are applied to control the read-out circuit 280. Under the control of the read-out circuit 280, data signals in the storage circuit 278 are read out to the digital data transmitter 282. The speed of readout from the storage circuit 278 is twice as fast as the speed at which signals are applied to the storage circuit. In addition, each word stored in the storage circuit 278 is read out twice during the period in which the next subsequent word is applied to the storage circuit.

Following transmission over the line 284, the received signals are coupled by the bridge circuit 286 to the two receiver channels 288 and 290. Channel 288 is coupled to the noise circuit 292 and the digital data receiver 294. The signals on channel 290 are delayed by one word period in the circuit 296, and are then applied to the noise circuit 298 and the digital data receiver 300. The timing circuit 302 enables the noise circuits 292 and 298 during the proper intervals to detect noise associated with information detected by the digital data receivers 294 and 300. The signals from the digital data receivers 294 and 300 are applied at a high pulse repetition rate during alternate word periods to the storage circuits 304 and 306. Under the control of the read-out circuit 308, word signals are read out from storage circuits 304 and 306 synchronously and at the desired slower pulse repetition rate. The receiving terminal in the circuit of Fig. 12 would also include the parity check and bit-by-bit comparator as well as other circuits which are shown at the righthand side of Fig. 1. In addition, the selection of channels A or B of Fig. 14 is accomplished in one of the manners discussed above for the circuit of Fig. 1.

In the foregoing detailed description, the present invention has been described in the context of systems in which each bit of digital information is transmitted twice. In an important sense, the present invention is also applicable to systems in which digital information is transmitted with a lesser degree of redundancy. For specic example, the situation will be considered in which the transmission of a series of code groups is followed by a. parity check summary code group. Table III, which is set forth below, indicates a typical set of code groups of this type.

Thus, for example, with reference to Table III, five code groups of six bits each are transmitted, and the sixth code -group is a summary parity check code group. 'Fhe sixth code group is made up of digits which individually check the parity of successive digits of each of the preceding code groups. Thus, for example, referring to Table lll, the first digit of the summary code group Iis a 1. Using an even parity check system, the first digit ofthe summary check group must be a 1 to make the total number of ls in the first column of Table III add up to an even number. The remaining digits of the sixth code group shown in Table III are formed in the same manner as described above for the first digit. As signals of the type shown in Table III are received and decoded, noise detection circuitry is also utilized. The noise detection circuitry lissimilar to that described above;

stieoi-ieally, noise signals .are detected `and iregistered sin accordance Awith ,the received signals with which they armassociated. In the presentsystem, for example, 1th? successive code groups may vbe employed :to m tape perforator, or lmay actually be used to produc typewritten characters at ,the receiver. Detected noise hits fontside the normal lsignal transmission .band `are detected and employedto markethereoeived record teindieate 4vthe `code .sgroup which was .heine reeeiyed :at eilte time the `mise hitoeenrred. Subsequently. .if the ntaryfparity cheek vindicates an error, the ,ertoneon received .information may readily be loeated ntllrou l, identification mentioned Labore. .Correetion lof th roneousfreoeived ldigit vis @then p ssible by Jthe idgnuicaf tion nf .thetoode group tin -wlnielithe noise shit (assorted. and the identification of the particular erroneous received bits avthroush :the ,snmrnarylparity cheek.

The einalits .des ined 'abone have sheen ,idisenssed 1in die context v.of a .reoeiyer :including vfe l.separate .eheels eirenitsi These V.eheelr ,oirenits include -ibitfhy-lai-t comparator .and the noise `.and .parity ,ebook circuits dior eaehof the two channels llt-.iste be nnderstoor1 tha `.the circuits `fare lalsoapulinable to situations tin whioh a :lesser n er fof 'output sneek y.signals are available for example, .a ,system eoold be arranged whioh .the noise fresnonsive cheek eironits are adjusted tto .a :relativ lyliiglrilerel sothattlney vare,energia/ed;,onlyhy relay severe noise hits- 'Under ftheseleronrnstanees. :the oodofimnairrnentofdata is high. andrtheltransmi ion of digital data to theiutilization Acircuit would be interrupted. In a similar manner, bit-by-bit comparison information could bewused ywith either parity check information or with noise check signals. Selection of one channel or interruption of the digital signals could then be made in much the same manner as is indicated in Table I. It is to be understood, however, that in a preferred embodiment of the invention, all tive check signals mutually cooperate to produce a far higher level of error elimination than is possible with any subcombinations of the over-all circuit.

It is to be understood that the above-described arrangements are illustrative of the application of the principles of the invention. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit and scope of the invention.

What is claimed is:

l. In a digital data handling system, a source of digital signals, said source including means for providing information digits and parity check digits for said information digits, two transmission channels, a transmitter for applying signals representing said information and parity digits 4to both of said two transmission channels, receiving apparatus coupled to said two transmission channels, a bit-by-bit comparison check circuit included in said receiving apparatus for checking the identity of received signals on said two channels, an individual parity check circuit associated with each channel in said receiving apparatus, a level responsive noise detection check circuit associated with each channel in said receiving apparatus, a digital information utilization circuit, switching circuits responsive to digital signals developed by said check circuits for coupling digital nformation from the one of said two channels which is most probably correct to said utilization circuit during successive time intervals, an alarm circuit, and additional switching circuits responsive to the digital signals developed by said check circuits for interrupting signal transmission to said utilization circuit and for energizing said alarm circuit when the digital information on both of said channels is probably erroneous.

2. In a digital data handling system, a source of digital signals, said source including means for providing information and check digits, a data link, transmitting means coupled to said source for applying said digital signals to said data link, decoding means coupled `14 to said :data link Ifor `Vobte ing l.error.eheolsins A.signals front .the `received sisnnlsta level actuated noise detee 'on circuit for producing .additional errorlchecking signals inldigital .forni in `-esponse to noise hits .on ysaidd ta and logic circuit means `:coupled to said 1`decoding means Vand fsa-id -noise detection circuit ,for Videntifying and eliminating errorsin the-,receiveddigital signals.H

-.3 lIn a disitaldata handling system, .a .soureeof .diei-tal signals, .said -sonree .inelndins ymeans for providing iinformation digits and parity' check digits f or said information digits, two.transmissionohannelsa transmitter `for applying signals representing fsaid information and paritydieits to both yof said ,two transmission ohannels, A a lreceiving apparatus It o,upled to Vsaid `two ,transm` ,ghahnnels a `Biolay-bit comparison check circuit linclud .in .said Ireceiving .apparatus for Aoli-eolrint' the identity/of received ,signals Qn ksaid -two channels, an individugl rarity Vcheek siren-it associated :with .each vChannel d rreceiving apparatus., a level responsiyenoise detention check circuit associated vwith each kchannel in Vsaid .t elying apparatus7 .a digital .information ,utiliz i. circuit. switching leireuits yfor selectively oontlasting t,said two channels to saidntilizationeirenit, and llogis .circuitry responsive to the .digital `signals developed :by said five ,ebook circuits .for v`energizing said switching eireults .for .eliminating erroneous received digital signals.

.4. .A .system asdefined-inelaim 3 wherein geographi- .eolly separated .transmission facilities are `provided for .said ntwo vtran.smission channels- 5. A system .as .defined .in .claim 3 `wherein.means are asrovlded .for shifting the freqneney .band .of `one .ofsaid Etransrnissionehannels.withlresneettotheotherohannel- 6. A system as defined in yclaim 3 lwherein means are provided for delaying digital signals applied to one of said channels with respect to the digital signals applied to the other channel.

7. In a digital data handling system, a source of digital signals, said source including means for providing information and check digits, a data link, transmitting means coupled to said source for applying said digital signals to said data link, decoding means coupled to said data link for obtaining error checking signals from the received signals, a level actuated spurious signal detection circuit for producing additional error checking signals in digital form in response to spurious signals on said data link, and logic circuit means coupled to said decoding means and said detection circuit for eliminating erroneous received digital signals.

8. In a digital data handling system, a digital data transmitter, a digital data receiver, a transmission channel intercoupling said transmitter and said receiver, an electrical delay component, a utilization circuit coupled to said receiver =by a circuit including said electrical delay component, a level actuated noise responsive bistalble circuit associated with said receiver for indicating the occurrence of severe noise hits on said channel, and switching circuit means responsive to output signals from said noise circuit for interrupting the circuit coupling said receiver to said utilization circuit to eliminate the digital signals subject to said noise hits.

9. In a digital data handling system, a digital data transmitter, a digital data receiver, a transmission channel intercoupling said transmitter and said receiver, a utilization circuit coupled to said receiver, a level actuated noise responsive bistable circuit associated with said receiver for indicating the occurrence of severe noise hits on said channel, and switching circuit means responsive to output signals from said noise circuit for interrupting the coupling between said receiver and -said utilization circuit to eliminate digital signals subject to `said noise hits.

10. In a digital data handling system, a source of digital signals, said source including means for providing information digits and parity check digits for said 4information digits, two transmission channels each having pre- 15Y assigned frequency transmission bands, a transmitter for applying signals representing said information and parity digits to both of said two transmission channels, a re# ceiving apparatus coupled to said two transmission channels, a bit-by-bit comparison check circuit included in said receiving apparatus for checking the identity of received signals on said two channels, an individual parity check circuit associated with each channel in said receiving apparatus, a level sensitive noise detection check circuit coupled to each channel in said receiving apparatus, filter circuit means included between said channels and said noise detection circuits for 'blocking digital signals in said pre- Vassigned frequency bands, a digital information utilization circuit, switching circuits responsive to digital signals .developed by said check circuits for coupling digital information from the one of said two channels which is most probably correct to said utilization circuit during successive time intervals, an alarm circuit, and additional switching circuits responsive to the digital signals developed by said check circuits for interrupting signal transmission to said utilization circuit and for energizing said alarm circuit when the digital information on both of said channels is probably erroneous.

11. yIn a digital data handling system, a source of digital signals,V said source including means for providing information and check digits, a data link, transmitting means coupled to said source for applying said digital signals to said data link, decoding means coupled to said data link for obtaining error checking signals from the received signals, level actuated noise detection circuit means responsive to noise hits on said data link outside thel signal transmission band for producing additional error checking signals in digital form, and logic circuit means coupled to said decoding means and said noise detection means for identifying errors in the received digital signals.

12. In a digital data handling system, means for providing redundant digital signals, a data link, a receiver, means for transmitting said redundant digital signals to said receiver over said data link, decoding means included in said receiver for obtaining error checking signals from the redundant received signals, a level actuated noise detection circuit for producing additional error checking signals in digital form in response to noise hits on said data link, and logic circuit means for detecting errors in the received digital signals in accordance with the error checking signals from said decoding means and said' noise detection circuit. 13. In a digital data handling system, a source of digital signals, two transmission channels, a transmitter for applying signals representative of said digital signals to both of said two transmission channels, a receiver coupled to said two transmission channels, a bit-by-bit comparison check circuit at said receiver for checking the identity of received signals on said two channels, a level responsive noise detection check circuit associated with each channel at said receiver, a digital information utilization circuit, switching circuits for selectively connecting said two channels to said utilization circuit, and logic circuitry responsive to the digital signals developed by said check circuits for energizing said switching circuits to eliminate erroneous received digital signals.

No references cited. 

